USB FPGA Prototype Board

This page contains information on the USBP FPGA prototype board.

Features

Xilinx Spartan3 400 FPGA
USB Interface, High Speed USB
- Configure FPGA through USB (JTAG connector also available)
- High speed USB (480Mbps) interface to FPGA
- PC USB drivers/library available
- Examples (HDL and PC software) to transfer USB to FPGA data
  - Xilinx Webpack for Verilog HDL synthesis
Basic Xilinx FPGA HDL examples available (blink LEDs, etc)
Fully powered through USB (no external power needed)
Code examples currently available at USBP.
Expansion Connector compatible with Digilent IO boards
Low Cost!!

USB FPGA Board

USB FPGA Development Board

Board can be purchased here here

Hardware and Software Questions can be posted on the forum

Introduction

The USB FPGA Prototype board has a Xilinx XC3S400. The FPGA is connected to the FX2 USB FIFO interface, LEDs, buttons, and the expansion connector. See below for more information on the available interfaces.

Cypress FX2 High Speed USB 2.0 Controller

The Cypress FX2 High Speed USB 2.0 controller is used to transfer data between the FPGA and the PC at rates up to 480Mbps. The FX2 also has an 8051 microcontroller which is used for various tasks including programming the FPGA and JTAG.

FPGA LEDs

There are 8 general purpose LEDs connected to the FPGA. These are useful for status indication.

Buttons

There are 2 user buttons on the board connect to the FPGA. See the example HDL and misc wiki pages for examples on using the buttons.

JTAG Connector

The JTAG connector is compatible with the Xilinx JTAG programmers.

Component Locations

FPGA Configuration

The FPGA can easily be configured through the USB interface.

Board Interface Software

The USBP project provides open-source code to interface to the board.

Clock Sources

The FPGA's main clock is received from the FX2's IFCLK (48MHz). This clock can be divided down or multiplied up using the FPGA's DCM.

Block Diagram and Power Distribution

FIXME

Expansion Connector Pinout

Pin	Name	FPGA Pin	Pin	Name	FPGA Pin
1	TDI		2	TDO
3	TMS		4	TCK
5	GPIO1	P79	6	GPIO0	P80
7	GPIO3	P77	8	GPIO2	P78
9	GPIO5	P74	10	GPIO4	P76
11	GPIO7	P70	12	GPIO6	P73
13	GPIO9	P68	14	GPIO8	P69
15	GPIO11	P60	16	GPIO10	P63
17	GPIO13	P58	18	GPIO12	P59
19	GPIO15	P56	20	GPIO14	P57
21	GPIO17	P53	22	GPIO16	P55
23	GPIO19	P51	24	GPIO18	P52
25	GPIO21	P47	26	GPIO20	P50
27	GPIO23	P44	28	GPIO22	P46
29	GPIO25	P40	30	GPIO24	P41
31	GPIO27	P35	32	GPIO26	P36
33	GPIO29	P32	34	GPIO28	P33
35	GPIO31	P30	36	GPIO30	P31
37	+3.3V		38	GPIO32	P28
39	GND		40	+5V

Expansion Connector Schematic

Schematics

Xilinx ISE constraints (UCF)

NET "HDR<0>"  LOC = P80    | IOSTANDARD=LVCMOS33 ;
NET "HDR<1>"  LOC = P79    | IOSTANDARD=LVCMOS33 ;
NET "HDR<2>"  LOC = P78    | IOSTANDARD=LVCMOS33 ;
NET "HDR<3>"  LOC = P77    | IOSTANDARD=LVCMOS33 ;
NET "HDR<4>"  LOC = P76    | IOSTANDARD=LVCMOS33 ;
NET "HDR<5>"  LOC = P74    | IOSTANDARD=LVCMOS33 ;
NET "HDR<6>"  LOC = P73    | IOSTANDARD=LVCMOS33 ;
NET "HDR<7>"  LOC = P70    | IOSTANDARD=LVCMOS33 ;
NET "HDR<8>"  LOC = P69    | IOSTANDARD=LVCMOS33 ;
NET "HDR<9>"  LOC = P68    | IOSTANDARD=LVCMOS33 ;
NET "HDR<10>" LOC = P63    | IOSTANDARD=LVCMOS33 ;
NET "HDR<11>" LOC = P60    | IOSTANDARD=LVCMOS33 ;
NET "HDR<12>" LOC = P59    | IOSTANDARD=LVCMOS33 ;
NET "HDR<13>" LOC = P58    | IOSTANDARD=LVCMOS33 ;
NET "HDR<14>" LOC = P57    | IOSTANDARD=LVCMOS33 ;
NET "HDR<15>" LOC = P56    | IOSTANDARD=LVCMOS33 ;
NET "HDR<16>" LOC = P55    | IOSTANDARD=LVCMOS33 ;
NET "HDR<17>" LOC = P53    | IOSTANDARD=LVCMOS33 ;
NET "HDR<18>" LOC = P52    | IOSTANDARD=LVCMOS33 ;
NET "HDR<19>" LOC = P51    | IOSTANDARD=LVCMOS33 ;
NET "HDR<20>" LOC = P50    | IOSTANDARD=LVCMOS33 ;
NET "HDR<21>" LOC = P47    | IOSTANDARD=LVCMOS33 ;
NET "HDR<22>" LOC = P46    | IOSTANDARD=LVCMOS33 ;
NET "HDR<23>" LOC = P44    | IOSTANDARD=LVCMOS33 ;
NET "HDR<24>" LOC = P41    | IOSTANDARD=LVCMOS33 ;
NET "HDR<25>" LOC = P40    | IOSTANDARD=LVCMOS33 ;
NET "HDR<26>" LOC = P36    | IOSTANDARD=LVCMOS33 ;
NET "HDR<27>" LOC = P35    | IOSTANDARD=LVCMOS33 ;
NET "HDR<28>" LOC = P33    | IOSTANDARD=LVCMOS33 ;
NET "HDR<29>" LOC = P32    | IOSTANDARD=LVCMOS33 ;
NET "HDR<30>" LOC = P31    | IOSTANDARD=LVCMOS33 ;
NET "HDR<31>" LOC = P30    | IOSTANDARD=LVCMOS33 ;
NET "HDR<32>" LOC = P28    | IOSTANDARD=LVCMOS33 ;

UCF File

Full UCF available here UCF File.

fpgaz/usbp/hw.txt · Last modified: 2009/02/27 07:44 by wiki_admin