USBP FPGA HDL

The main HDL block discussed here is the FX2 FIFO interface.

To leverage other open-source work the FIFO interface implemented in the FPGA will be an FX2 Slave FIFO to Wishbone.

There are 2 different data paths. One is intended to look and feel like a memory mapped interface. This is the wishbone bus, the Slave FIFO interface will pass data to the wishbone master. When additional wishbone blocks are added it is pretty simple to program them. For us embedded and FPGA developers this will probably feel very natural. In the USBP_LIB and address, data API will be available.

More encapsulation can/will be added to the PC software. But a low level interface will be accessible.

The second data path is intended to be lower overhead. Similar FIFO data path. Even though there may exist multiple pipeline stages the max through put is intended to match 48/96 MB/sec.

FX2 Slave FIFO Interface

This module does a fair amount of work. It monitors the 8 FIFOS, 4 from FX2 and 4 internally. Then it will transfer data from one FIFO to the next. This will add extra delay (pipeline) but the overall throughput should be able to be sustained.

* EP2 WB PortA * WB PortB EP6 * EP4 iFIFO PortA * iFIFO PortB EP8

The intended timing diagrams

Read

Read and Write

Both the read and write transactions have a couple extra cycles at the beginning of a transfer. Ones a burst of bytes gets going should maintain max throughput. Basically fits USB data tranfer type, bursty chunks of data.

TODO: Simulation Waveforms / Results TODO: Captured Waveforms

FX2 -> Wishbone

Provide a simple address data interface to the internal wishbone bus. For more information on the wishbone bus see http://www.opencores.org/projects.cgi/web/wishbone/wishbone OpenCores website. Again the wishbone interface was a simple choice cause HDL cores from the opencores website can be used.

Example if we wanted to add a simple SPI port we can simply grab one from opencores. Yes an SPI isn't that difficult but can take a little time to add all the features of programmable clock phase data latching edges, etc. Also more complicated cores can be used.

FX2 -> Decicated FIFO path

As mentioned there are 2 different data paths. One is mapped to the wishbone interface (and of course this can all be changed by modifing the HDL). The other is intended to be a dedicated data path. Example if a CMOS imager is interfaced, the wishbone interface can be used for configuration but the second FIFO interface can be used specifically for transferring data.