A basic Analog to Digital Converter (LTC1096, that I had laying around) is interfaced to the USBP FPGA Protype Board. The LTC1096 has a simple syncronouos serial interface.

The basic ADC configuration was used and the CLK_IN and DATA_OUT signals were wired to the expansion connector.

LTC1096 Datasheet

The following table shows the connections made.

The FPGA is designed around a control (EP2/EP6) and data (EP4/EP8) path. The EP2/EP6 Out/In pairs map to a wishbone bus. There is a simple commands structure to send address data pairs to the FPGA circuit.

In this example the EP4/EP8 Out/In pairs are use. These pairs are mapped to an async FIFO in the FPGA (async FIFO if for potential different clock bondraries). There is a simple circuit that will drive the clock read the sample and send it to the FIFO. The USB FX2 FIFO interface will then read the data out of the FPGA async FIFO and send it to the FX2 controller to be passed to the PC.

The firmware is the same fw for most applications. The firmware will configure the FX2 for slave FIFO mode.

The software will continuously poll the USB endpoints for data, retrieving 512 byte packets.

import USBP
c = USBP.UFO400()
c.initUSB()
 
c.loadFxFirmware('usbp_v1.hex')
 
c.configFPGA('usbp_top.bit')
 
# Enable ADC, need to write more than 1 byte
d = [0xF0]*4 + [0xF5]*4
c.WriteData(d)
 
# Start Reading Data from the USBP Board
rd = [0]*512
for i in range(100)
    c.ReadData(rd, 512)
    print rd
 
# Disable ADC
d = [0xFA]*4
c.WriteData(d)

The following is a flash movie that shows a sinusoid generated by a function generator, fed into the ADC, input displayed on the scope, and the retrieved data view with matplotlib. The scope was captured with a (low res) USB camera. The short video shows the data received follows the signal on the scope.

def adc():
    global c
    print 'Enable ADC...'
    # Simple command to enable ADC
    d =[0xF0]*4 + [0xF5]*4
    c.WriteData(d)
 
    # Start Reading Samples, init read buffer
    #rd = range(32)
    rd = [0]*512
 
    print 'Read Samples...'
    for i in range(200):
        err = c.ReadData(rd)
        pylab.plot(rd,hold=False)
        pylab.show()
        if(err != 0):
            print err
            print rd
            time.sleep(2)
            break
 
    print rd    
    # Disable ADC capture
    d =[0xFA]*4
    c.WriteData(d)
 
    # Make sure all data read
    for i in range(10):
        err = c.ReadData(rd)
        if(err != 0):
            break

Expansion Connector compatible with Digilent IO boards