Some information for the USBP project is available on the USBP wiki.  Some of the information has been out dated and is being posted on this blog.  The USBP project provides a C/C++ library that wraps generic USB drivers and provides some canned functions (example configuring an FPGA).  The USBP project also provides a Python wrapper for the library.  The Python class also adds additional functionality.

The USBP Python provides a flexible environment for interfacing with USB FPGA boards.  The Python module can also be used interactively.  It can be useful to peek and poke wishbone registers interactively.

The following is a very basic Python example to open an interface to an USB FPGA board.  Different boards are support.

>>> import usbp
>>> usb = usbp.USBP("ufo400")

# Load the FX2 Firmware
>>> usb.LoadFxFirmware('usbp_v1.hex')   

# Configure the FPGA on the Development Board
>>> usb.ConfigFPGA('usbp_top.bit')

Using they Python USBP class is very simple and provides additional functions to send and receive data, read/write to the wishbone bus and read/write to the I2C bus on the USB controller.

Introduction

This project is an audio echo implementation on the
DSPtronics mixed-signal FPGA module. The board is great for experimenting with Audio DSP on an FPGA. The board includes and Audio CODEC and some additional analog for single-bit ADC and DAC.

DSPtronics provides the Verilog to configure and interface to the audio CODEC. If you own a board the audio CODEC interface Verilog can be requested from here.

Audio Echo

This project implements a simple echo by delaying the audio stream and adding the delayed signal with the non-delayed signal. The audio format used is 24bit @ 96kHz. The implementation provides a 170ms delay.  The internal FPGA BRAM is utilized for the delay. The amount of BRAM used determines the max delay.  The delay is programmable from the register interface, from no delay to the max delay.
To get some additional delay only 10bits are used and the delayed signal is divided by 2.
This first part implements a simple echo, later different delay paths (filtering the delay) path
will be explored.

MyHDL and Verilog Top-Level

For this example MyHDL was used to implement the echo logic. The top-level is coded in Verilog and the DSPtronics audio CODEC was provided in Verilog source.

Converting to Verilog

The MyHDL is converted to Verilog and then the generated Verilog is added to the ISE project. To generate the Verilog simply type the following at a command line.

  \$ python dsp_echo.py

A link to the source is available at the end of this file.

Synthesis and PaR

The design can be run through the Xilinx tools.

Loading the Bitfile onto the Board

Once the bit-file has been created the USBP library can be used to download the bit-file or the “programmer” application provided by DSPtronics can be used to download the bit file. To download the bit-file using the USBP Python interface the following can be typed at a console or entered into a script.

  \$ python

  >>> import USBP

  >>> usb = USBP.USBP('dspes')

  >>> usb.ConfigFpga('signa-x1.bit')

The bit-file will be configured to the FPGA and the echo will start running as soon as the bit-file configuration is complete. The configuration will also toggle the LEDs so it should be obvious if the bit-file configured successfully or not.

DSPtronics Programmer Download Bit-File

Echo in Action

Here the sounds.

Files

• MyHDL Source
• Top-Level Verilog
• UCF File